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LH5164AVH
FEATURES * 8,192 x 8 bit organization * Access time: 200 ns (MAX.) * Supply current (MAX.): Operating: 90 mW 29 mW (tRC, tWC = 1 s) Standby: 3.6 W (MAX.) @ 70C 10.8 W (MAX.) @ 85C Data retention: 0.6 W (VCC = 3 V, tA = 25C) * Low voltage operation: 3.3 V 0.3 V * Fully-static operation * TTL compatible I/O * Three-state outputs * Packages: 28-pin, 450-mil SOP 28-pin, 8 x 13 mm2 TSOP (Type I) DESCRIPTION
The LH5164AVH is a static RAM organized as 8,192 x 8 bits. It is fabricated using silicon-gate CMOS process technology.
OE A11 A9 A8 CE2 WE VCC NC A12 A7 A6 A5 A4 A3
CMOS 64K (8K x 8) Static RAM
PIN CONNECTIONS
28-PIN SOP TOP VIEW
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE CE2 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4
5164AVH-1
Figure 1. Pin Connections for SOP Package
28-PIN TSOP (Type I)
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2
5164AVH-2
Figure 2. Pin Connections for TSOP Package
1
LH5164AVH
CMOS 64K (8K x 8) Static RAM
A9 24 A8 25 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 ROW SELECT MEMORY ARRAY (256 x 256) 28 VCC 14 GND
I/O1 11 I/O2 12 I/O3 13 I/O4 15 I/O5 16 I/O6 17 I/O7 18 I/O8 19
COLUMN I/O CIRCUITS INPUT DATA CONTROL
COLUMN SELECT
WE 27
OE 22 CE2 26 CE1 20 8 A2 NOTE: Pin numbers apply to the 28-pin SOP. 9 A1 10 A0 23 A11 21 A10
5164AVH-3
Figure 3. LH5164AVH Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A12 CE1/CE2 WE OE
Address inputs Chip Enable input Write Enable input Output Enable input
I/O1 - I/O8 VCC GND NC
Data inputs and outputs Power supply Ground No connection
2
CMOS 64K (8K x 8) Static RAM
LH5164AVH
TRUTH TABLE
CE1 CE2 WE OE MODE I/O1 - I/O8 SUPPLY CURRENT NOTE
H X L L L
NOTE: 1. X = H or L
X L H H H
X X L H H
X X X L H
Standby Write Read Output disable
High-Z Data input Data output High-Z
Standby (ISB) Operating (ICC) Operating (ICC) Operating (ICC)
1 1
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Supply voltage Input voltage Operating temperature Storage temperature
VCC VIN Topr Tstg
-0.3 to +7.0 -0.3 to VCC +0.3 -40 to +85 -65 to +150
V V C C
1 1, 2
NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. VIN (MIN.) = -3.0 V for pulse width 50 ns.
RECOMMENDED OPERATING CONDITIONS (TA = -40C to +85C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Supply voltage Input voltage
VCC VIH VIL
3.0 VCC - 0.5 -0.3
3.3
3.6 VCC + 0.3 0.2
V V V 1
NOTE: 1. VIL (MIN.) = -3.0 V for pulse width 50 ns.
DC CHARACTERISTICS 1 (TA = -40C to +85C, VCC = 3.3 V 0.3 V)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Input leakage current Output leakage current Operating supply current
ILI ILO
VIN = 0 V to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = 0 to VCC CE 1 = 0.2 V, VIN = 0.2 V, or VCC - 0.2 V CE2 = VCC - 0.2 V, Outputs open CE2 0.2 V or CE1 VCC - 0.2 V CE1 = VIH or CE2 = VIL IOL = 500 A IOH = -500 A tCYCLE = 200 ns tCYCLE = 1.0 s TA +70C TA +85C
-1.0 -1.0
1.0 1.0 25
A A
ICC
mA 8 1.0 3.0 5 0.4 VCC - 0.5 A mA V V
Standby current
ISB ISB1 VOL
1
Output voltage VOH
NOTE: 1. CE2 should be VCC - 0.2 V or 0.2 V when CE1 VCC - 0.2 V.
3
LH5164AVH
CMOS 64K (8K x 8) Static RAM
READ CYCLE (TA = -40C to +85C, VCC = 3.3 V 0.3 V)
PARAMETER SYMBOL MIN. MAX. UNIT
Read cycle time Address access time CE 1 access time CE 2 access time Output enable access time Output hold time CE 1 Low to output in Low-Z CE 2 High to output in Low-Z OE Low to output in Low-Z CE 1 High to output in High-Z CE 2 Low to output in High-Z OE High to output in High-Z
tRC tAA tACE1 tACE2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ
200 200 200 200 150 10 20 20 10 0 0 0 60 60 40
ns ns ns ns ns ns ns ns ns ns ns ns
WRITE CYCLE (TA = -40C to +85C, VCC = 3.3 V 0.3 V)
PARAMETER SYMBOL MIN. MAX. UNIT
Write cycle time CE Low to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Input data setup time Input data hold time WE High to output in Low-Z WE Low to output in High-Z OE High to output in High-Z
tWC tCW tAW tAS tWP tWR tDW tDH tOW tWZ tOHZ
200 180 180 0 150 0 100 0 20 0 0 60 40
ns ns ns ns ns ns ns ns ns ns ns
TEST CONDITIONS
PARAMETER MODE NOTE
Input pulse level Input rise/fall time Input/output timing level Output load
0.2 V to VCC - 0.2 V 10 ns 1.5 V CL (100 pF) 1
NOTE: 1. Includes scope and jig capacitance.
CAPACITANCE 1 (TA = 25C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Input capacitance I/O capacitance
CIN CI/O
VIN = 0 V VI/O = 0 V
7 10
pF pF
NOTE: 1. This parameter is sampled and not production tested.
4
CMOS 64K (8K x 8) Static RAM
LH5164AVH
DATA RETENTION CHARACTERISTICS (TA = -40C to +85C)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Data retention supply voltage
VCCDR
CE2 0.2 V or CE1 VCCDR - 0.2 V VCCDR = 3 V, CE2 0.2 V or CE1 VCCDR - 0.2 V TA = 25C TA = 70C
2.0 0.2 0.6 1.5
V A A A ns ns
1
Data retention supply current
ICCDR
1
Chip disable to data retention Recovery time
tCDR tR
0 tRC
2
NOTES: 1. CE2 should be VCCDR - 0.2 V or 0.2 V. 2. t RC = Read cycle time.
CE1 CONTROL (NOTE) DATA RETENTION MODE VCC 3.0 V tCDR tR
VCC - 0.5 V VCCDR CE1 VCCDR - 0.2 V CE1 0V
CE2 CONTROL DATA RETENTION MODE VCC 3.0 V CE2 tCDR tR
VCCDR 0.2 V 0V CE2 0.2 V
NOTE: To control the data retention mode at CE1, fix the input level of CE2 between VCCDR to VCCDR - 0.2 V or 0 V and 0.2 V during the data retention mode.
5164AVH-7
Figure 4. Data Retention Characteristics
5
LH5164AVH
CMOS 64K (8K x 8) Static RAM
tRC
A0 - A12 tAA tACE1
CE1 tLZ1 tACE2 tHZ1
CE2 tLZ2 tOE tOLZ tHZ2
OE tOHZ
DOUT
DATA VALID tOH
NOTE: WE = 'HIGH.'
5164AVH-4
Figure 5. Read Cycle
6
CMOS 64K (8K x 8) Static RAM
LH5164AVH
tWC
A0 - A12
OE tAW tCW (NOTE 1) CE1 tCW tWR tWR (NOTE 2)
CE2 tAS (NOTE 3) WE tOHZ tWP (NOTE 4) tWR
DOUT tDW (NOTE 5) tDH
DIN
DATA VALID
NOTES: 1. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 2. tWR is defined as the time from writing finish to address change. 3. tAS is defined as the time from address change to writing start. 4. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 5. When I/O pins are in the output state, input signals with the opposite logic level must not be applied.
5164AVH-5
Figure 6. Write Cycle (OE Controlled)
7
LH5164AVH
CMOS 64K (8K x 8) Static RAM
tWC
A0 - A12 tAW tCW (NOTE 1) CE1 tCW tWR tWR (NOTE 2)
CE2 tAS (NOTE 3) WE tWZ (NOTE 5) DOUT tDW (NOTE 7) DATA VALID tDH tOW (NOTE 6) tWP (NOTE 4) tWR
DIN
NOTES: 1. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 2. tWR is defined as the time from writing finish to address change. 3. tAS is defined as the time from address change to writing start. 4. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 6. If CE1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the outputs will remain high-impedance. 7. When I/O pins are in the output state, input signals with the opposite logic level must not be applied.
5164AVH-6
Figure 7. Write Cycle (OE Low Fixed)
8
CMOS 64K (8K x 8) Static RAM
LH5164AVH
PACKAGE DIAGRAMS
28SOP (SOP028-P-0450)
1.27 [0.050] TYP. 1.70 [0.067] 15 8.80 [0.346] 8.40 [0.331] 12.40 [0.488] 11.60 [0.457]
0.50 [0.020] 0.30 [0.012]
28
10.60 [0.417]
1 18.20 [0.717] 17.80 [0.701]
14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
28SOP
28-pin, 450-mil SOP
9
LH5164AVH
CMOS 64K (8K x 8) Static RAM
28TSOP (TSOP028-P-0813)
0.28 [0.011] 0.12 [0.005] 28 0.55 [0.022] TYP. 15
12.00 [0.472] 11.60 [0.457]
13.70 [0.539] 13.10 [0.516]
12.60 [0.496] 12.20 [0.480]
1 8.20 [0.323] 7.80 [0.307]
14 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] 0.425 [0.017] 1.10 [0.043] 0.90 [0.035] 0.20 [0.008] 0.00 [0.000]
28TSOP
DETAIL
0 - 10
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
28-pin, 8 x 13 mm2 TSOP (Type I)
ORDERING INFORMATION
LH5164AVH Device Type
X Package
N 28-pin, 450-mil SOP (SOP028-P-0450) T 28-pin, 8 x 13 mm2 TSOP (Type I) (TSOP028-P-0813) CMOS 64K (8K x 8) Static RAM
Example: LH5164AVHN (CMOS 64K (8K x 8) Static RAM, 28-pin, 450-mil SOP)
5164AVH-8
10

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